This invention relates to integrated circuits and methods of their fabrication; and more particularly the invention relates to field-effect transistors and methods for fabricating their gate.
In the prior art, the gates of field-effect transistors were fabricated by depositing an unpatterned layer of polycrystalline silicon on an insulating layer over a surface of a semiconductor wafer. This silicon layer was deposited in a polycrystalline state (as opposed to an amorphous state) to increase its stability and conductivity. Subsequently, the silicon layer was patterned by removing selected portions of it to form a gate.
One problem, however, with this prior art process, is that the thickness of the polycrystalline silicon layer cannot be uniformly controlled across the wafer. Typically, the thickness variations are large enough to cause a substantial portion (e.g.--20%) of the wafer's surface to be unuseable. This unuseable portion generally occurs at the wafer's perimeter.
Another problem with the above prior art process is that the accuracy with which the edge of the transistor's gate can be defined is limited by the orientation of the polycrystals. That is, both a plasma etch and a wet chemical etch attack various portions of the polycrystalline layer at different rates depending upon the grain boundaries of the layer. This then places a limitation on the accuracy with which the gate's edge can be reproduced.
Still another problem with the above described prior art process, is that on a microscopic level, a deposited polycrystalline surface is not smooth; but instead it contains thousands of hillhocks. These hillhocks, in turn, can lower the adhesion between the gate and any overlying material; and they also can lower the breakdown voltage of the patterned polycrystalline layer.
Accordingly, a primary object of this invention is to provide an improved field-effect transistor and method of fabricating the same.
Another object of the invention is to provide an improved method of fabricating a patterned polycrystalline silicon layer in an integrated circuit.